Shift Register question: 595 165 parallel operation possible like in Shurthi XT


it has been a long time since i last did ask a question, now that i a lot of the synthesizer stuff running, not yet into modular, probably never will be but anyhow:

I did see that the parallel to seriell ICs 74HC165 and the respective 74HC595 do use the same SPI lines of the atmel chip, am I right?

I got curious since I am starting to built some hardware around those chips as well, and I was curious to simply use the SPI hardware module insetad of slow software bitbanging.

I just have those two ICs hooked up together but I think the 595 and the 165 do have different behaviour in their (mutabel calles it) IO_ENABLE, I will call it CS for chipselect.

the 595 the IO_ENABLE needs to be lowso that the data is clocked thrugh
the 165 needs to be high in order to shift the data out

So question is, am I doing something wrong, can some signals be inversed, could I simply use an inverter or 2 different CS signals for each device, or did mutable do something i dont see right now to achieve the parallel behaviour.

OR of course pretty straight forward: dont use those two ICs in parallel but one after another.

Thanks for reading my sometimes confusing thoughts.
And thanks for advice.



Simple solution: dont use them in parralel.



The Shruthi doesn’t do bit-banging, and does use the SPI hardware. Why? Because the SPI hardware only takes ownership of the MISO, MOSI and SCK lines. That’s true on AVR and on the STM32F chips too. As for the CS line, you’re free to use any pin you want and it’s up to you to control it. I don’t call it CS because as you’ve correctly noticed, it doesn’t always behave like a CS (low during a transfer, high otherwise). So I prefer continuing calling it IO_ENABLE.

I don’t use any inverter.

When I want to read the 165s:

  • I strobe the IO_ENABLE line (quickly set it from high to low back to high). This causes the 165 to load its data.
  • I do one SPI read per byte of data to be read. The SPI hardware correctly shifts the data in on the MISO and SCKlines. Whatever happens with MOSI is ignored by the 595 because the IO_ENABLE (connected to its RCLK pin) remains high during the transfer.

When I want to write to the 595s:

  • I set IO_ENABLE low.
  • I do my writes. The SPI hardware shifts things out on the MOSI and SCK lines. Because IO_ENABLE is low, the 165 won’t read and shift any data.
  • I set IO_ENABLE high.


thanks for the quick answer, I know I could count on that :slight_smile:

That is what I assumed, so either a wrtie operation or a read operation.

Or as I could also implement, I code on the texas MSP430, the CS is also a GPIO, so I could use 2 different CS pins and use those 2 chips in parallel.
Of course we are talking with a 1 MHz clock of about 9 us time savings, so I guess it wont be worth the effort.

Thanks for making it clear.
Have a nice week.