Plaits Normalization Probe


#1

Hello!

Longtime lurker, first time poster :slight_smile: My name is Tenkai, and I run Zetaohm. I released a sequencer last year named FLXS1, and I referenced mutable designs for so many things during the design process. So, thank you Olivier for your contributions! I was at Superbooth 2017, and hoped to meet you, but thats when you were sick and unable to attend.

Anywho, I wanted to ask about something I saw in the Plaits ADC input design. You have a “Normalization Probe” and I just wanted to verify with you what I assume is going on, and also have a question…

It appears that this circuit is designed to allow you to actively sense the connection of a cable into any of the ports by pinging the normalization input of all ADCs simultaneously (between ADC reads, I assume) with a 3v3 signal.

My question is:

With the 1n caps on some of the ADC inputs, and a .2ms settling time for a 3v3 ping, how are you able to achieve a 2khz DC input, and also check for normalization? I would assume that checking for normalization would require that a ping be sent, and one ADC sample would be lost.


#2

The “normalization probe” signal is pseudo-random noise, generated at the same rate as the ADC sampling.

If ADC reads match the pseudo-random noise (no more than 2 mismatches in 32 consecutive reads), I know that no patch cable is inserted in the corresponding input. https://github.com/pichenettes/eurorack/blob/master/plaits/ui.cc#L368

Nothing happens “in-between” samples.

The ADC sample rate is 4kHz (250µs), and the 90% settling time of the 1-pole filter on the CV inputs (33kΩ, 1nF) is 76µs.


#3

Ah, that makes sense! So you can simply use the same read operation to determine if the jack is connected or not. That is quite ingenious. Thank you for the explanation!


#4

This IS clever…