Longtime lurker, first time poster My name is Tenkai, and I run Zetaohm. I released a sequencer last year named FLXS1, and I referenced mutable designs for so many things during the design process. So, thank you Olivier for your contributions! I was at Superbooth 2017, and hoped to meet you, but thats when you were sick and unable to attend.
Anywho, I wanted to ask about something I saw in the Plaits ADC input design. You have a “Normalization Probe” and I just wanted to verify with you what I assume is going on, and also have a question…
It appears that this circuit is designed to allow you to actively sense the connection of a cable into any of the ports by pinging the normalization input of all ADCs simultaneously (between ADC reads, I assume) with a 3v3 signal.
My question is:
With the 1n caps on some of the ADC inputs, and a .2ms settling time for a 3v3 ping, how are you able to achieve a 2khz DC input, and also check for normalization? I would assume that checking for normalization would require that a ping be sent, and one ADC sample would be lost.