ATmega328P Firmware Upload Lock-Bits Setting

A bit tangential, this, but I’ve just re-flashed the ATmega MCU on a non-MI DIY Euro module with the latest firmware, but I’m a bit worried about one of the settings I used, which someone on another forum suggested might have caused the chip be hard to re-flash in the future.

These are the avrdude commands I used:

avrdude -V -p m328p -c usbtiny -B 10 -e -u \\
-U efuse:w:0x05:m \\
-U hfuse:w:0xde:m \\
-U lfuse:w:0xff:m \\
-U lock:w:0x2f:m

Followed by:

avrdude -V -p m328p -c usbtiny -B 1 -U flash:w:prizma_v2.hex:i -U lock:w:0x2f:m

I based the commands on those detailed in the CVPal documentation, but obviously that project uses a different MCU. Everything seemed to work fine with the flashing process, but is the lock-bit setting (0x2f) incorrect for this chip, or likely to cause me problems in the future?

Sorry for the probably silly question, but like many, it seems, I struggle with the whole firmware programming side of Synth DIY projects, and I’m finding the many tutorials I’ve looked at have generally left me more confused than before, sadly.


What exactly did this person say that would make it hard to reflash? As long as the clock source is set correctly and the ISP interface is not disabled, all should be fine. (yes there is a bit that entirely shuts down the ISP interface, making it practically impossible to reprogram the chip, but many GUI tools don’t even let you change it to prevent accidents.)

There are online tools to generate the lock bit patterns from a human-readable list of settings. Some tools can also so the reverse. That can help you understand what the bits actually mean

Hi @TheSlowGrowth thanks for getting back to me. They said that with those particular lock bit settings a ‘high voltage’ programmer might be required if I needed to to re-flash the MCU later.

I’m not sure that’s the case though, as the first command set lock bits this way, and I didn’t have any problem actually uploading the hex file with the next command.


Yes, the high voltage programmer is the only way to regain access to the chip after its JTAG and ISP interfaces are disabled. If the firmware upload worked, then the ISP interface is still active. So nothing to worry about.

Cool! That’s good to know.

Do you happen to know what what a lock bits setting of ‘2f’ actually means though?

In future, would it be best just to use a lock bit setting of ‘ff’, (presumably) disabling all locks?


I dont know off the top of my head. Try this tool, it will give you all the details

Choosing the lock bits must be done carefully. For example, many applications need the JTAG interface disabled to be able to use the corresponding pins for something else. In essence, the bits configure the basic conditions under which the processor starts up and does its work - things like security features, clock settings, programming interfaces, power monitoring, etc. For any given project, there is pretty much just one valid bit combination. Its not something you can tweak or adjust freely

I see. Unfortunately, for this particular project, the developer specified the other fuse bits, but not the lock bit settings.